Vertical memory devices
US10242997B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2016 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Jul 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.