Vertical josephson junction superconducting device
US10243132B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2018 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Mar 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N60/805
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Techniques for a vertical Josephson junction superconducting device are provided. In one embodiment, a chip surface base device structure is provided that comprises a substrate comprising crystalline silicon that is coupled with a first superconducting layer, wherein the first superconducting layer is coupled with a second substrate comprising crystalline silicon. In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in an etched region of the substrate, the vertical Josephson junction comprising a first superconducting layer, a tunnel barrier layer, and a top superconducting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.