Enhancement mode FET gate driver IC
US10243546B2 · kind B2 · utility
3Cited by
4References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 2017 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | May 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/01
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fully integrated GaN driver comprising a digital logic signal inverter, a level shifter circuit, a UVLO circuit, an output buffer stage, and (optionally) a FET to be driven, all integrated in a single package. The level shifter circuit converts a ground reference 0-5 V digital signal at the input to a 0-10 V digital signal at the output. The output drive circuitry includes a high side GaN FET that is inverted compared to the low side GaN FET. The inverted high side GaN FET allows switch operation, rather than a source follower topology, thus providing a digital voltage to control the main FET being driven by the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.