Run time ECC error injection scheme for hardware validation
US10248521B2 · kind B2 · utility
5Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2016 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Sep 16, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for a run-time error correction code (“ECC”) error injection scheme for hardware validation are disclosed. The systems and methods include configuring a read path to internally forward read data, and injecting at least one faulty bit into the forwarded read data via a read fault injection logic. The systems and methods may also include configuring a write path to internally forward write data, and injecting at least one faulty bit into the forwarded write data via a write fault injection logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.