Integrated circuit simulation with variability analysis for efficient memory usage
US10248745B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2017 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Jun 9, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for simulating an integrated circuit design is provided. The method includes forming a partition of an IC netlist into blocks based on a performance value from at least a portion of a parameter space and forming a table with parameter values including multiple instances of at least one block of the partition. The computer-implemented method also includes analyzing a direct-current (DC) solution of at least one block by combining at least a first instance of a first block with a second instance of a second block based on the performance value from the portion of the parameter space, and performing a transient analysis where signals change over time for the at least one block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.