Configurable pseudo dual port architecture for use with single port SRAM

US10249363B2 · kind B2 · utility

Assignee

• STMicroelectronics International N.V. · NL

Inventors

• Harsh Rawat · Faridabad, IN
• Abhishek Pathak · Kathiatoli, IN

Key dates

• Filing date: Jun 26, 2018
• Grant date: Apr 2, 2019
• Expiry date: Jun 26, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/418
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.