Harsh Rawat
23Patents
2h-index
20Co-inventors
53Inventor score
Filing activity: Nov 11, 2009 → Oct 12, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8144537B2 | Balanced sense amplifier for single ended bitline memory architecture | Physics | 9 | Active |
| US9311990B1 | Pseudo dual port memory using a dual port cell and a single port cell with associated valid data bits and related methods | Physics | 5 | Active |
| US8458545B2 | Method and apparatus for testing of a memory with redundancy elements | Physics | 2 | Active |
| US10032506B2 | Configurable pseudo dual port architecture for use with single port SRAM | Physics | 2 | Active |
| US11984151B2 | Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 1 | Active |
| US12087356B2 | Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 1 | Active |
| US12040013B2 | Static random access memory supporting a single clock cycle read-modify-write operation | Physics | 1 | Active |
| US12361982B2 | Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode | Physics | 0 | Active |
| US12340099B2 | Static random access memory supporting a single clock cycle read-modify-write operation with a modulated word line assertion | Physics | 0 | Active |
| US10249363B2 | Configurable pseudo dual port architecture for use with single port SRAM | Physics | 0 | Active |
| US12354644B2 | Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 0 | Active |
| US9524242B2 | Cache memory system with simultaneous read-write in single cycle | Physics | 0 | Active |
| US12159689B2 | SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applications | Physics | 0 | Active |
| US12068026B2 | Low power and fast memory reset | Physics | 0 | Active |
| US12353341B2 | Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection | Physics | 0 | Active |
| US12183424B2 | Bit-cell architecture based in-memory compute | Physics | 0 | Active |
| US9786364B1 | Low voltage selftime tracking circuitry for write assist based memory operation | Physics | 0 | Active |
| US9208040B2 | Repair control logic for safe memories having redundant elements | Physics | 0 | Active |
| US12170120B2 | Built-in self test circuit for segmented static random access memory (SRAM) array input/output | Physics | 0 | Active |
| US12176025B2 | Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 0 | Active |
| US12237007B2 | Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Physics | 0 | Active |
| US12406705B2 | In-memory computation circuit using static random access memory (SRAM) array segmentation | Physics | 0 | Active |
| US12046324B2 | Modular memory architecture with gated sub-array operation dependent on stored data content | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.