Semiconductor memory device
US10249377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2017 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Sep 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, a sense amplifier, a word line, and a row decoder. A write operation repeats a program loop including a program operation, first and second verify operations. The row decoder applies a first read voltage to the word line in the first and second verify operations. When the write operation is not suspended, the sense amplifier senses a voltage of the bit line for a first sense period in the first verify operation. When the write operation is suspended, the sense amplifier senses the voltage of the bit line for a second sense period shorter than the first sense period in the initial first verify operation after a resumption of the write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.