Redistribution layer structure of semiconductor package
US10249567B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 25, 2017 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Dec 25, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A redistribution layer structure of the semiconductor package includes a dielectric layer having a thickness, at least one upper conductive wire disposed on a first surface of the dielectric layer, at least one lower conductive wire disposed on a second surface of the dielectric layer, and vias penetrating the dielectric layer and connecting the at least one upper conductive wire and the at least one lower conductive wire. Each via has a cross-section at one upper conductive wire. The cross-section has a third width. The ratio of the third width to the thickness of the dielectric layer is less than or equal to 1. The ratio of the pitch between every two adjacent vias to the third width is greater than or equal to 0.5.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.