Single-stage CMOS-based voltage quadrupler circuit
US10250133B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 2017 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Jul 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356104
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A single stage voltage quadrupler circuit includes a first capacitive voltage boosting circuit responsive to a first clock signal and operable to boost a voltage at a first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially two times the first voltage level. A pass transistor selectively passes the boosted voltage at the first node to a second node in response to a control signal generated by a bootstrapping capacitor circuit in response to the level shifted first clock signal. A second capacitive boosting circuit is operable to boost the voltage at the second node in response to a level shifted second clock signal that is the logical invert of the level shifted first clock signal to third voltage level that is substantially four times the first voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.