Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network
US10250262B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 2018 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Feb 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising a plurality of logic tiles, wherein each logic tile (i) is physically adjacent to at least one other logic tile of the plurality and (ii) includes a configurable switch interconnect network including a plurality of switches electrically interconnected and arranged into a plurality of switch matrices, wherein the plurality of switch matrices are arranged into a plurality of stages including: (a) at least two of the stages which is configured in a hierarchical network, and (b) a mesh stage, wherein each switch matrix of the mesh stage includes an output that is directly connected to an input of a plurality of different switch matrices of the mesh stage and wherein the mesh stage of switch matrices of each logic tile is directly connected to the mesh stage of switch matrices of at least one other logic tile of the plurality of the logic tiles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.