Flex Logix Technologies, Inc.
51Patents
51Active
51Granted
54Portfolio score
Filing activity: May 14, 2015 → Dec 8, 2022
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9543958B1 | Multiplexer-memory cell circuit, layout thereof and method of manufacturing same | Electricity | 12 | Active |
| US10523209B1 | Test circuitry and techniques for logic tiles of FPGA | Electricity | 9 | Active |
| US9503092B2 | Mixed-radix and/or mixed-mode switch matrix architecture and integrated circuit, and method of operating same | Electricity | 6 | Active |
| US9240791B2 | Clock distribution architecture for logic tiles of an integrated circuit and method of operation thereof | Electricity | 6 | Active |
| US9973194B2 | Block memory layout and architecture for programmable logic IC, and method of operating same | Physics | 5 | Active |
| US9496876B2 | Clock distribution architecture for logic tiles of an integrated circuit and method of operation thereof | Electricity | 5 | Active |
| US10693469B2 | Multiplier-accumulator circuit, logic tile architecture for multiply-accumulate, and IC including logic tile array | Electricity | 4 | Active |
| US10411711B2 | FPGA having a virtual array of logic tiles, and method of configuring and operating same | Electricity | 4 | Active |
| US9882568B2 | Clock distribution architecture for logic tiles of an integrated circuit and method of operation thereof | Electricity | 4 | Active |
| US10587271B2 | Clock distribution and generation architecture for logic tiles of an integrated circuit and method of operating same | Electricity | 4 | Active |
| US9786361B1 | Programmable decoupling capacitance of configurable logic circuitry and method of operating same | Electricity | 4 | Active |
| US10972103B2 | Multiplier-accumulator circuitry, and processing pipeline including same | Electricity | 4 | Active |
| US9906225B2 | Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network | Electricity | 4 | Active |
| US11693625B2 | Logarithmic addition-accumulator circuitry, processing pipeline including same, and methods of operation | Electricity | 4 | Active |
| US11314504B2 | Multiplier-accumulator processing pipelines and processing component, and methods of operating same | Physics | 3 | Active |
| US10855284B1 | Process of routing tile-to-tile interconnects of an FPGA, and method of manufacturing an FPGA | Electricity | 3 | Active |
| US10778228B1 | Reconfigurable data processing pipeline, and method of operating same | Electricity | 3 | Active |
| US9793898B2 | Mixed-radix and/or mixed-mode switch matrix architecture and integrated circuit, and method of operating same | Electricity | 3 | Active |
| US10348308B2 | Clock architecture, including clock mesh fabric, for FPGA, and method of operating same | Electricity | 3 | Active |
| US11277135B2 | Process of routing tile-to-tile interconnects of an FPGA, and method of manufacturing an FPGA | Electricity | 2 | Active |
| US10250262B2 | Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network | Electricity | 2 | Active |
| US9755651B2 | Multiplexer-memory cell circuit, layout thereof and method of manufacturing same | Electricity | 2 | Active |
| US11288076B2 | IC including logic tile, having reconfigurable MAC pipeline, and reconfigurable memory | Electricity | 2 | Active |
| US10886922B2 | Test circuitry and techniques for logic tiles of FPGA | Electricity | 1 | Active |
| US11194585B2 | Multiplier-accumulator circuitry having processing pipelines and methods of operating same | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.