PVT compensated resistive biasing architecture for a capacitive sensor
US10250999B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2017 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Sep 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04R2201/003
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit for biasing a MEMS microphone includes a first group of serially-coupled transistors coupled between a first node and a second node, a second group of serially-coupled transistors coupled between the first node and the second node, and a voltage divider circuit coupled to the second node having a number of outputs, a first group of outputs being coupled to corresponding control nodes associated with the first group of serially-coupled transistors, and a second group of outputs different from the first group of outputs coupled to corresponding control nodes associated with the second group of serially-coupled transistors, the control nodes being either bulk nodes or gate nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.