Modifying design layer of integrated circuit (IC) using nested and non-nested fill objects
US10254642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2018 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Jan 31, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.