Veeresh V. Deshpande
33Patents
3h-index
31Co-inventors
55Inventor score
Filing activity: Sep 12, 2014 → Dec 21, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9570169B1 | Resistive memory device | Physics | 21 | Active |
| US10657440B2 | Optical synapse for neuromorphic networks | Physics | 4 | Active |
| US10516108B2 | Tunable resistive element | Physics | 3 | Active |
| US10312441B1 | Tunable resistive element | Physics | 3 | Active |
| US9786664B2 | Fabricating a dual gate stack of a CMOS structure | Electricity | 2 | Active |
| US10546992B2 | Buried electrode geometry for lowering surface losses in superconducting microwave circuits | Electricity | 2 | Active |
| US9984929B1 | Fabricating contacts of a CMOS structure | Electricity | 2 | Active |
| US11157807B2 | Optical neuron | Physics | 2 | Active |
| US10395732B2 | Resistive memory apparatus using variable-resistance channels with high- and low-resistance regions | Physics | 2 | Active |
| US9977325B2 | Modifying design layer of integrated circuit (IC) | Physics | 1 | Active |
| US11521055B2 | Optical synapse | Physics | 1 | Active |
| US9917164B1 | Fabricating raised source drain contacts of a CMOS structure | Electricity | 1 | Active |
| US9997409B1 | Fabricating contacts of a CMOS structure | Electricity | 1 | Active |
| US9953125B2 | Design/technology co-optimization platform for high-mobility channels CMOS technology | Electricity | 1 | Active |
| US11138501B2 | Hardware-implemented training of an artificial neural network | Physics | 1 | Active |
| US10254642B2 | Modifying design layer of integrated circuit (IC) using nested and non-nested fill objects | Physics | 1 | Active |
| US10395168B2 | Tunable optical neuromorphic network | Physics | 1 | Active |
| US9881921B2 | Fabricating a dual gate stack of a CMOS structure | Electricity | 1 | Active |
| US10304934B2 | Fabricating raised source drain contacts of a CMOS structure | Electricity | 1 | Active |
| US10103234B1 | Fabricating raised source drain contacts of a CMOS structure | Electricity | 0 | Active |
| US9451684B2 | Dual pulse driven extreme ultraviolet (EUV) radiation source method | Electricity | 0 | Active |
| US9704757B1 | Fabrication of semiconductor structures | Electricity | 0 | Active |
| US9673104B1 | Fabrication of a CMOS structure | Electricity | 0 | Active |
| US9923022B2 | Array of optoelectronic structures and fabrication thereof | Electricity | 0 | Active |
| US10037800B2 | Resistive memory apparatus using variable-resistance channels with high- and low-resistance regions | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.