External clock based clock generator
US10254783B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Aug 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generation circuit includes a delay chain configured to generate an N-number of clock signals at a frequency multiple that is M-times the frequency of a reference clock signal. To generate the clock signals at the frequency multiple, a multiplexer selectively inputs, to the delay chain, a delayed reference clock signal and a last clock signal generated by a last delay cell of the delay chain. In addition, a delay control generator circuit periodically compares the phases of the delayed reference clock signal and the last clock signal to set the delay of the delay chain. The clock generation circuit generates the N-number of clock signals at the frequency multiple in response to receipt of the reference clock signal, and continues to generate the clock signals at the frequency multiple when the reference clock signal is no longer being received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.