Apparatus and method for a hybrid latency-throughput processor
US10255077B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2016 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Aug 2, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7892
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.