Apparatus and method for obfuscating power consumption of a processor

US10255462B2 · kind B2 · utility

Assignee

• Arm Limited · GB

Inventors

• Bal S. Sandhu · Fremont, US
• George McNeil Lattimore · Austin, US
• Carl Wayne Vineyard · Cedar Park, US

Key dates

• Filing date: Jun 17, 2016
• Grant date: Apr 9, 2019
• Expiry date: May 13, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L2209/125
• WIPO field: Control
• WIPO sector: Instruments

Abstract

An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. The second power consumption varies inversely with the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The counterbalance circuitry and the header circuitry are each coupled to the logic circuitry at the common node.