George McNeil Lattimore
78Patents
18h-index
67Co-inventors
87Inventor score
Filing activity: Aug 2, 1993 → Nov 29, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6134164A | Sensing circuit for a memory cell array | Physics | 408 | Expired |
| US7466607B2 | Memory access system and method using de-coupled read and write circuits | Physics | 193 | Expired |
| US6157216A | Circuit driver on SOI for merged logic and memory circuits | Electricity | 136 | Expired |
| US5581734A | Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity | Physics | 71 | Expired |
| US6243776A | Selectable differential or single-ended mode bus | Physics | 57 | Expired |
| US9514814B1 | Memory write driver, method and system | Physics | 48 | Active |
| US5877976A | Memory system having a vertical bitline topology and method therefor | Physics | 38 | Expired |
| US5892372A | Creating inversions in ripple domino logic | Electricity | 31 | Expired |
| US5831896A | Memory cell | Physics | 31 | Expired |
| US9748943B2 | Programmable current for correlated electron switch | Electricity | 29 | Active |
| US5467037A | Reset generation circuit to reset self resetting CMOS circuits | Electricity | 28 | Expired |
| US6915385B1 | Apparatus for unaligned cache reads and methods therefor | Emerging Cross-Sectional Technologies | 28 | Expired |
| US6058065A | Memory in a data processing system having improved performance and method therefor | Physics | 22 | Expired |
| US6021512A | Data processing system having memory sub-array redundancy and method therefor | Physics | 20 | Expired |
| US5953745A | Redundant memory array | Physics | 20 | Expired |
| US9979385B2 | Circuit and method for monitoring correlated electron switches | Physics | 19 | Active |
| US9851738B2 | Programmable voltage reference | Physics | 19 | Active |
| US6477635B1 | Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasing | Physics | 19 | Expired |
| US6640293B1 | Apparatus and method of utilizing Alias Hit signals to detect errors within the real address tag arrays | Physics | 18 | Expired |
| US9805777B2 | Sense amplifier | Electricity | 18 | Active |
| US5896399A | System and method for testing self-timed memory arrays | Physics | 17 | Expired |
| US9786370B2 | CES-based latching circuits | Electricity | 17 | Active |
| US5956286A | Data processing system and method for implementing a multi-port memory cell | Physics | 10 | Expired |
| US5812418A | Cache sub-array method and apparatus for use in microprocessor integrated circuits | Physics | 10 | Expired |
| US9142266B2 | Memory circuitry using write assist voltage boost | Physics | 10 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.