No miss cache structure for real-time image transformations with multiple LSR processing engines
US10255891B2 · kind B2 · utility
2Cited by
16References
21Claims
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Key dates
| Filing date | Apr 12, 2017 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Apr 12, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed herein for providing improved cache structures and methods that are optimally sized to support a predetermined range of late stage adjustments and in which image data is intelligently read out of DRAM and cached in such a way as to eliminate re-fetching of input image data from DRAM and minimize DRAM bandwidth and power. The systems and methods can also be adapted to work with compressed image data and multiple LSR processing engines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.