Semiconductor device with tiered pillar and manufacturing method thereof
US10256114B2 · kind B2 · utility
11Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2017 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Mar 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.