Semiconductor wafer dicing crack prevention using chip peripheral trenches
US10256149B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2017 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Feb 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54453
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor base substrate having a substantially planar growth surface is provided. A first type III-V semiconductor layer is epitaxially grown on the growth surface. First and second trenches that vertically extend from an upper surface of the first type III-V semiconductor layer at least to the growth surface are formed. The first and second trenches are filled with a filler material that is different from material of the type III-V semiconductor layer. A cut that separates the first type III-V semiconductor layer and the base substrate into two discrete semiconductor chips is formed. The cut is formed in a lateral section of the first type III-V semiconductor layer that is between the first and second trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.