Overlapping stacked die package with vertical columns
US10256208B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2014 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Oct 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some forms relate to an electronic assembly (10) that includes a die (11) that includes an upper surface (12) and a conductive column (13) extending from the upper surface (12) such that the conductive column (13) is not surrounded by any material other than where the conductive column (13) engages the die (11). Other forms relate to an electronic package (19) that includes a stack (20) of electronic assemblies (10) where each electronic assembly (10) includes a die (11) that having an upper surface (12) and a plurality of conductive columns (13) extending from the upper surface (12) such that each conductive column (13) is not surrounded by any material other than where the conductive column (13) engages the die (11), and wherein the stack (20) of electronic assemblies (10) is arranged in an overlapping configuration such the plurality of conductive columns (13) on each electronic assembly (10) are not covered by another electronic assembly (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.