Cheng Yang
23Patents
4h-index
26Co-inventors
59Inventor score
Filing activity: Sep 26, 2007 → Dec 22, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8017183B2 | Organosiloxane materials for selective area deposition of inorganic materials | Chemistry; Metallurgy | 30 | Active |
| US8030212B2 | Process for selective area deposition of inorganic materials | Electricity | 16 | Active |
| US7846644B2 | Photopatternable deposition inhibitor containing siloxane | Physics | 5 | Active |
| US11189622B1 | Semiconductor device with graphene layer and method for forming the same | Electricity | 4 | Active |
| US8129098B2 | Colored mask combined with selective area deposition | Electricity | 3 | Active |
| US10620221B2 | Devices and assays for diagnosis of sinusitis | Physics | 2 | Active |
| US10629561B2 | Overlapping stacked die package with vertical columns | Electricity | 2 | Active |
| US11682603B2 | Control of thermal interface material in multi-chip package | Electricity | 1 | Active |
| US10256208B2 | Overlapping stacked die package with vertical columns | Electricity | 1 | Active |
| US12243850B2 | Devices, systems, and methods for stacked die packages | Electricity | 0 | Active |
| US11652151B2 | Semiconductor device structure with fine conductive contact and method for preparing the same | Electricity | 0 | Active |
| US11521978B2 | Semiconductor device and method for fabricating the same | Electricity | 0 | Active |
| US12368324B2 | Inductive coupling system and method for adaptive control of power transfer for wireless three-dimensional stacked chip package | Electricity | 0 | Active |
| US11304302B2 | Methods of creating exposed cavities in molded electronic devices | Electricity | 0 | Active |
| US12237209B2 | Method of manufacturing memory device having active area in elongated block | Electricity | 0 | Active |
| US9936582B2 | Integrated circuit assemblies with molding compound | Emerging Cross-Sectional Technologies | 0 | Active |
| US11723151B2 | Methods of creating exposed cavities in molded electronic devices | Electricity | 0 | Active |
| US11114448B2 | Semiconductor device and method for fabricating the same | Electricity | 0 | Active |
| US12278138B2 | Method of manufacturing memory device with first and second isolation members using patterned photoresist layer and energy-decomposable mask | Electricity | 0 | Active |
| US11270974B2 | Embedded copper structure for microelectronics package | Electricity | 0 | Active |
| US11114536B1 | Semiconductor device having multiple dimensions of gate structures and method for fabricating the same | Electricity | 0 | Active |
| US10896877B1 | System in package with double side mounted board | Electricity | 0 | Active |
| US11699734B2 | Semiconductor device with resistance reduction element and method for fabricating the same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.