Patent · US Active

Reduced-height electronic memory system and method

US10256213B2 · kind B2 · utility

1Cited by

1References

13Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Eng Huat Goh · Air Itam, MY
Min Suet Lim · Kampung Bukit Kechil, MY
Jiun Hann Sir · Air Itam, MY

Key dates

Filing date	Dec 10, 2015
Grant date	Apr 9, 2019
Priority date	—
Expiry date	Dec 10, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/18161
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A computer memory module can include a molded layer disposed on a DRAM substrate. The molded layer can encapsulate a DRAM die and wire bonds that connect the DRAM die to the DRAM substrate, and can be shaped to include at least one cavity having a footprint sized to accommodate a system on chip (SOC) die. The DRAM module can attach to an SOC package so that the SOC die and the DRAM die are both positioned between the DRAM substrate and the SOC package, the DRAM substrate can form its electrical connections on only one side of the DRAM substrate, and the SOC die can fit at least partially into the cavity in the molded layer. This can reduce a package Z-height, compared to conventional DRAM packages in which the SOC die and the DRAM die are positioned on opposite sides of the DRAM substrate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.