Vertical transmon qubit device
US10256392B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2018 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Mar 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N60/805
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Techniques for a vertical transmon qubit device are provided. In one embodiment, a chip surface base device structure is provided that comprises a first superconducting material physically coupled to a crystalline substrate, wherein the crystalline substrate is physically coupled to a second superconducting material, wherein the second superconducting material is physically coupled to a second crystalline substrate. In one implementation, the chip surface base device structure also comprises a vertical Josephson junction located in a via of the crystalline substrate, the vertical Josephson junction comprising the first superconducting material, a tunnel barrier, and the second superconducting material. In one implementation, the chip surface base device structure also comprises a transmon qubit comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.