Cascode switch circuit including level shifter
US10256811B2 · kind B2 · utility
2Cited by
17References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2017 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Aug 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0175
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.