Wafer-level package having one die with its clock source shared by multiple dies and associated clock generating method
US10261928B2 · kind B2 · utility
4Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2018 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Jun 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/005
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A wafer-level package includes a first die and a second die that are wafer-level packaged. The first die has a first clock source. The second die has a second clock source. The first clock source generates a clock shared by the first die and the second die. The second clock source, however, does not generate a clock used by any of the first die and the second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.