DRAM having a plurality of registers
US10262718B2 · kind B2 · utility
7Cited by
56References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Dec 27, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a memory device includes a clock receiver to receive a clock signal and a plurality of mode registers to store parameter information associated with a plurality of operating clock frequencies of the clock signal. The plurality of clock frequencies include a first clock frequency and a second clock frequency. The memory device also includes a command interface to receive commands synchronously with respect to the clock signal. The command interface receives a command that instructs the DRAM device to change operation from the first clock frequency to the second clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.