Stacked silicon package having a thermal capacitance element
US10262920B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2016 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Dec 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73253
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Chip packages and electronic devices are provided that include a thermal capacitance element that improves the operation of IC dies at elevated temperatures. In one example, a chip package is provided that includes an integrated circuit (IC) die, a lid thermally connected to the IC die, and a thermal capacitance element thermally connected to the lid. The thermal capacitance element includes a container and a capacitance material sealingly disposed in the container. The capacitance material has a phase transition temperature that is between 80 and 100 percent of a maximum designed operating temperature in degrees Celsius of the IC die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.