Reversible semiconductor die
US10262926B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2016 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Oct 5, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die has internal circuitry formed on two more internal layers, and die bonding pads arranged on a top surface of the die. The bonding pads are connected to the internal circuitry for providing input and output signals to the internal circuitry. One or more connecting lines electrically connect one or more pairs of the die bonding pads, thereby defining a bonding pad layout. The die bonding pads are arranged and connected with the connecting lines such that the bonding pad layout is reversible, which allows the die to be used in different package types (e.g., TSSOP or DFN) yet maintain a standardized pin arrangement without the necessity for long or crossed bond wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.