Integrated circuit, system for and method of forming an integrated circuit
US10262981B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Mar 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/975
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit is disclosed. The method includes generating, by a processor, a layout design of the integrated circuit, outputting the integrated circuit based on the layout design, and removing a portion of a conductive structure of the integrated circuit to form a first conductive structure and a second conductive structure. Generating the layout design includes generating a standard cell layout having a set of conductive feature layout patterns, placing a power layout pattern with the standard cell layout according to at least one design criterion, and extending at least one conductive feature layout pattern of the set of conductive feature layout patterns in at least one direction to a boundary of the power layout pattern. The power layout pattern includes a cut feature layout pattern. The cut feature layout pattern identifies a location of the removed portion of the conductive structure of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.