Semiconductor memory device and method of manufacturing the same
US10263008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2016 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Aug 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0234
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.