Patent · US Active

Method of fabricating a FET transistor having a strained channel

US10263077B1 · kind B1 · utility

7Cited by

3References

12Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Shay Reboh · Grenoble, FR
Remi Coquand · Chambéry, FR

Key dates

Filing date	Dec 22, 2017
Grant date	Apr 16, 2019
Priority date	—
Expiry date	Dec 22, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/822
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Method for fabricating at least one FET transistor (100a, 100b) comprising:

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.