Inventor · Grenoble, FR

Shay Reboh

62Patents

4h-index

43Co-inventors

58Inventor score

Filing activity: Aug 7, 2014 → Mar 14, 2022

Most-cited inventions

Patent	Title	Area	Cited by	Status
US10263077B1	Method of fabricating a FET transistor having a strained channel	Electricity	7	Active
US10217849B2	Method for making a semiconductor device with nanowire and aligned external and internal spacers	Electricity	6	Active
US11081547B2	Method for making superimposed transistors	Electricity	6	Active
US9431538B2	Enhanced method of introducing a stress in a transistor channel by means of sacrificial sources/drain regions and gate replacement	Electricity	5	Active
US10205021B1	Method of fabrication of a semiconductor substrate having at least a tensilely strained semiconductor portion	Electricity	4	Active
US9876121B2	Method for making a transistor in a stack of superimposed semiconductor layers	Electricity	4	Active
US9502558B2	Local strain generation in an SOI substrate	Electricity	4	Active
US10269930B2	Method for producing a semiconductor device with self-aligned internal spacers	Electricity	4	Active
US9246006B2	Recrystallization of source and drain blocks from above	Electricity	4	Active
US10896956B2	Field effect transistor with reduced contact resistance	Electricity	3	Active
US10431683B2	Method for making a semiconductor device with a compressive stressed channel	Electricity	3	Active
US10217842B2	Method for making a semiconductor device with self-aligned inner spacers	Electricity	3	Active
US9761607B2	Method for producing strained semi-conductor blocks on the insulating layer of a semi-conductor on insulator substrate	Electricity	2	Active
US10147818B2	Enhanced method of stressing a transistor channel zone	Electricity	2	Active
US10347721B2	Method to increase strain in a semiconductor region for forming a channel of the transistor	Electricity	2	Active
US10115590B2	Manufacturing of silicon strained in tension on insulator by amorphisation then recrystallisation	Electricity	2	Active
US9899217B2	Method for producing a strained semiconductor on insulator substrate	Electricity	2	Active
US9966453B2	Method for doping source and drain regions of a transistor by means of selective amorphisation	Electricity	2	Active
US9935019B2	Method of fabricating a transistor channel structure with uniaxial strain	Electricity	2	Active
US10141424B2	Method of producing a channel structure formed from a plurality of strained semiconductor bars	Electricity	2	Active
US10014183B2	Method for patterning a thin film	Electricity	2	Active
US10600786B2	Method for fabricating a device with a tensile-strained NMOS transistor and a uniaxial compression strained PMOS transistor	Electricity	2	Active
US9704709B2	Method for causing tensile strain in a semiconductor film	Electricity	2	Active
US9343375B2	Method for manufacturing a transistor in which the strain applied to the channel is increased	Electricity	2	Active
US10170621B2	Method of making a transistor having a source and a drain obtained by recrystallization of semiconductor	Electricity	2	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.