Buffer regions for blocking unwanted diffusion in nanosheet transistors
US10263100B1 · kind B1 · utility
61Cited by
15References
20Claims
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Assignee
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Key dates
| Filing date | Mar 19, 2018 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Mar 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0188
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method includes performing fabrication operations to form a nanosheet field effect transistor device. The fabrication operations include forming a sacrificial nanosheet and a channel nanosheet over a substrate, forming a diffusion barrier layer between the sacrificial nanosheet and the channel nanosheet, wherein a diffusion coefficient of the diffusion barrier layer is selected to substantially prevent a predetermined semiconductor material from diffusing through the diffusion barrier layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.