Method for managing the operation of a synchronous retention flip-flop circuit exhibiting an ultra-low leakage current, and corresponding circuit
US10263603B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 17, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Mar 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The synchronous retention flip-flop circuit comprises a first circuit module suitable for being powered by an interruptible power source and a second circuit module suitable for being powered by a permanent power source. The first circuit module includes first and second latch stages, which are configured to store at least one datum while said interruptible power source is supplying power, transmitting means suitable for being controlled by a second control signal and configured to deliver said at least one datum to the second circuit module before an interruption of said interruptible power source, the second circuit module being configured to preserve said at least one datum during said interruption, and restoring means suitable for being controlled by a first control signal and configured to restore said at least one datum at the end of said interruption. Only the second control signal remains active during interruption of the interruptible power source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.