Error correction and decoding
US10263645B2 · kind B2 · utility
2Cited by
28References
22Claims
0Family size
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Key dates
| Filing date | Sep 26, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Sep 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an embodiment, an error detection and correction apparatus includes a positive edge triggered flip-flop that receives syndrome input based on a syndrome output a syndrome generator indicating whether or not input data includes an error, whereby the positive edge triggered flip-flop further provides a syndrome output to an error location decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.