Continuous time linear equalization
US10263815B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2017 |
| Grant date | Apr 16, 2019 |
| Priority date | — |
| Expiry date | Dec 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1774
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This disclosure relates generally to continuous time linear equalization. In an example of a continuous time linear equalizer, a variable gain circuit includes transistors having gate nodes respectively as a first and a second input node. A first transimpedance circuit is connected between the first input node and a first output node. A second transimpedance circuit is connected between the second input node and a second output node. A source node of each of the first transistor and the second transistor are commonly connected to one another. In the same or another equalizer, output nodes of a first frequency peaking circuit are connected to input nodes of a second frequency peaking circuit. In such a same or another equalizer, an RC feedback circuit has tap-off nodes and summing nodes respectively connected at the output nodes of the first frequency peaking circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.