Apparatus and method for multi-bit error detection and correction
US10268539B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2015 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Jan 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/27
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are described for multi-bit error correction and detection. For example, one embodiment of a processor comprises: error detection logic to detect one or more errors in data when reading the data from a storage device, the data being read from the storage device with parity codes and error correction codes (ECCs); error correction logic to correct the errors detected by the error detection logic; and a matrix usable by both the error detection logic to detect the one or more errors and the error correction logic to correct the errors, the matrix constructed into N regions, each region having M columns forming a geometric sequence, wherein each successive region is a shifted version of a prior region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.