Patent · US Active

System, apparatus and method for prefetch-aware replacement in a cache memory hierarchy of a processor

US10268600B2 · kind B2 · utility

2Cited by

1References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Jayesh Gaur · Bengaluru, IN
Sreenivas Subramoney · Bengaluru, IN
Sanjay Ganapathy · Chennai, IN

Key dates

Filing date	Sep 12, 2017
Grant date	Apr 23, 2019
Priority date	—
Expiry date	Oct 3, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/62
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, a processor includes: a first cache controller to control a first cache memory. This cache controller may include a replacement circuit to: associate a first priority indicator with a first cache line based on storage of demand data in the first cache line and first learning information associated with a set of demand-based categories of cache lines; and associate a second priority indicator with a second cache line based on storage of prefetch data in the second cache line and second learning information associated with a set of prefetch-based categories of cache lines. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.