Patent · US Active

Architectural physical synthesis

US10268797B2 · kind B2 · utility

7Cited by

15References

20Claims

0Family size

Assignee

SYNOPSYS, INC. · US

Inventors

Kenneth S. McElvain · Los Altos, US
Benoit Lemonnier · Palo Alto, US
William Halpin · Palo Alto, US

Key dates

Filing date	Nov 21, 2013
Grant date	Apr 23, 2019
Priority date	—
Expiry date	Nov 21, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Methods and apparatuses to design an integrated circuit are discussed. In one embodiment, the method of designing an integrated circuit comprises partitioning a chip resource into a plurality of sections, and calculating the rank of the sections based on a quality metric. The method further comprises removing the sections with the lowest ranks from consideration by a placement transform.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.