Post write erase conditioning
US10269439B2 · kind B2 · utility
0Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2017 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Apr 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3495
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.