Inventor · Santa Clara, CA, US

Mohan Dunga

60Patents
13h-index
56Co-inventors
83Inventor score

Filing activity: Sep 19, 2008 → Apr 15, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US7755946B2 Data state-based temperature compensation during sensing in non-volatile memory Physics 43 Active
US9972396B1 System and method for programming a memory device with multiple writes without an intervening erase Physics 35 Active
US9202579B2 Compensation for temperature dependence of bit line resistance Physics 27 Active
US9935050B2 Multi-tier three-dimensional memory devices including vertically shared source lines and method of making thereof Electricity 24 Active
US9543028B2 Word line dependent temperature compensation scheme during sensing to counteract cross-temperature effect Physics 24 Active
US8988939B2 Pre-charge during programming for 3D memory using gate-induced drain leakage Physics 23 Active
US10115459B1 Multiple liner interconnects for three dimensional memory devices and method of making thereof Physics 23 Active
US10319680B1 Metal contact via structure surrounded by an air gap and method of making thereof Electricity 17 Active
US10008273B2 Cell current based bit line voltage Physics 17 Active
US9711231B1 System solution for first read issue using time dependent read voltages Physics 16 Active
US8988937B2 Pre-charge during programming for 3D memory using gate-induced drain leakage Physics 16 Active
US9142305B2 System to reduce stress on word line select transistor during erase operation Physics 14 Active
US8861282B2 Method and apparatus for program and erase of select gate transistors Electricity 13 Active
US9704588B1 Apparatus and method for preconditioning currents to reduce errors in sensing for non-volatile memory Physics 12 Active
US7974133B2 Robust sensing circuit and method Physics 11 Active
US9082502B2 Bit line and compare voltage modulation for sensing nonvolatile storage elements Physics 10 Active
US9368222B2 Bit line pre-charge with current reduction Electricity 8 Active
US9564226B1 Smart verify for programming non-volatile memory Physics 8 Active
US10304551B2 Erase speed based word line control Physics 7 Active
US10971240B1 Wordline smart tracking verify Physics 6 Active
US9443597B2 Controlling dummy word line bias during erase in non-volatile memory Physics 5 Active
US10643695B1 Concurrent multi-state program verify for non-volatile memory Physics 5 Active
US9159406B2 Single-level cell endurance improvement with pre-defined blocks Physics 5 Active
US10541031B2 Single pulse SLC programming scheme Physics 5 Active
US10559370B2 System and method for in-situ programming and read operation adjustments in a non-volatile memory Physics 4 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.