Method of manufacturing packaged wafer
US10269639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2017 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Mar 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/3185
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a method of manufacturing a packaged wafer including a step of forming grooves in a face side of a wafer along projected dicing lines to a depth larger than a finished thickness of the wafer, a step of forming a ring-shaped groove in and along a boundary between a device area and an outer peripheral excess area of the wafer to a depth larger than the depth of the grooves, and a step of placing a recess mold of a molding apparatus in engagement with the wafer so that a side wall of the recess mold is placed on a bottom of the ring-shaped groove and filling a space between the recess mold and the wafer with a molding resin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.