Device-manufacturing scheme for increasing the density of metal patterns in inter-layer dielectrics
US10269699B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2018 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Jan 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.