Semiconductor device and method
US10269704B2 · kind B2 · utility
3Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2018 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | May 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.