Method for manufacturing semiconductor structure
US10269737B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2017 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Oct 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor structure include: providing a die including a die pad disposed over the die; disposing a conductive member over the die pad of the die; forming a molding surrounding the die and the conductive member; disposing a dielectric layer over the molding, the die and the conductive member; and forming an interconnect structure including a land portion and a plurality of via portions. The land portion is disposed over the dielectric layer, the plurality of via portions are disposed over the conductive member and protruded from the land portion to the conductive member through the dielectric layer, and each of the plurality of via portions at least partially contacts with the conductive member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.