Stacked integrated circuits with redistribution lines
US10269768B2 · kind B2 · utility
9Cited by
26References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2016 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Dec 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.