High voltage transistor structure and method
US10269959B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2017 |
| Grant date | Apr 23, 2019 |
| Priority date | — |
| Expiry date | Oct 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/663
Abstract
A device comprises a buried layer over a substrate, a first well over the buried layer, a first high voltage region and a second high voltage region extending through the first well, a first drain/source region in the first high voltage region, a first gate electrode over the first well, a first spacer on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer on a second side of the first gate electrode, a second drain/source region in the second high voltage region and a first isolation region in the second high voltage region and between the second drain/source region and the first gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.